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rev: 1.01 11/2000 1/32 ? 2000, giga semiconductor, inc. specifications cited are design targets and are subject to change without notice. for latest documentation contact your gsi representative. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 2m x 9, 1m x 18 , 512k x 36 separate i/o sigma s dr sram 333 mhz 1.8 v v dd 1.8 v and 1.5 v i/ 209-bump bga commercial temp industrial temp s ram features ? observes the sigma ram pinout standard ? 1.8 v +150/?100 mv core power supply ? 1.5 v or 1.8 v i/o supply ? pipelined read operation ? fully coherent read and write pipelines ? echo clock outputs track data output drivers ? zq mode pin for user-selectable output drive strength ? 2 user-programmable chip enable inputs for easy depth expansion ? ieee 1149.1 jtag-compatible boundary scan ? 209-bump, 14 mm x 22 mm, 1 mm bump pitch bga package ? pin compatible with future 32m, 64m and 128m devices sigma ram family overview the gs8180 s 09/18 /36 b are built in compliance with the sigma ram pinout standard for separate i/o synchronous srams. they are 18,874,368-bit (16mb) srams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. gsi's family of common i/o s rams are offered in a number of configurations that emulate other synchronous srams, such as burst rams, nbt rams, late write, or double data rate (ddr) srams. the logical differences between the protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering, and write cueing. s rams allow a user to implement the interface protocol best suited to the task at hand. functional description because a sigma ram is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. because the separate i/o s ram always transfers data in two packets, a0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. since the lsb is tied off internally, the address field of a separate i/o s dr s ram is always one address pin less than the advertised index depth (e.g., the 1m x 18 has a 512k addressable index). single data rate (sdr) separate i/o sigma rams implement a pipelined read and incorporate a rising-edge-triggered output register. for read cycles, a pipelined sram?s output data is temporarily stored by the edge-triggered output register during the access cycle, and then released to the output drivers at the next rising edge of clock. gs818x18/36b s rams are implemented with gsi's high performance cmos technology and are packaged in a 209- bump bga. - 333 pipeline mode tkhkh 3.0 ns tkhqv 1.5 ns 209-bump, 14 mm x 22 mm bga 1 mm bump pitch, 11 x 19 bump array bottom view
rev: 1.01 11/2000 2/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 8180 s 36 pinout 512k x 36 separate i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a dc1 dc2 a e2 a (16m) mcl a (8m) e3 a qb1 qb2 b dc3 dc4 mcl nc a w a mcl nc qb3 qb4 c dc5 dc6 nc mcl nc (128m) e1 nc nc mcl qb5 qb6 d dc7 dc8 v ss nc nc mcl nc nc v ss qb7 qb8 e dc9 qc1 v ddq v ddq v dd v dd v dd v ddq v ddq db1 qb9 f qc3 qc2 v ss v ss v ss zq v ss v ss v ss db2 db3 g qc5 qc4 v ddq v ddq v dd ep2 v dd v ddq v ddq db4 db5 h qc7 qc6 v ss v ss v ss ep3 v ss v ss v ss db6 db7 j qc9 qc8 v ddq v ddq v dd m4 v dd v ddq v ddq db8 db9 k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l dd9 dd8 v ddq v ddq v dd m2 v dd v ddq v ddq qa8 qa9 m dd7 dd6 v ss v ss v ss m3 v ss v ss v ss qa6 qa7 n dd5 dd4 v ddq v ddq v dd mch v dd v ddq v ddq qa4 qa5 p dd3 dd2 v ss v ss v ss mcl v ss v ss v ss qa2 qa3 r qd9 dd1 v ddq v ddq v dd v dd v dd v ddq v ddq qa1 da9 t qd7 qd8 v ss nc nc mcl nc nc v ss da8 da7 u qd5 qd6 nc a nc (64m) a nc (32m) a nc da6 da5 v qd3 qd4 a (2m) a a a1 a a a (4m) da4 da3 w qd1 qd2 tms tdi a mcl a tdo tck da2 da1 rev 10 11 x 19 bump bga?14 x 22 mm2 body?1 mm bump pitch?ms-028vbc ? note: users of cmos i/o sigma rams may wish to connect d4, d8, t4, t8 and k4 to v ddq /2 to allow alternate use of hstl i/o sigma rams.
rev: 1.01 11/2000 3/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 8180 s 18 pinout 1m x 18 separate i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a db1 db2 a e2 a (16m) mcl a (8m) e3 a nc nc b db3 db4 mcl nc a w a nc nc nc nc c db5 db6 nc nc nc (128m) e1 a nc mcl nc nc d db7 db8 v ss nc nc mcl nc nc v ss nc nc e db9 qb1 v ddq v ddq v dd v dd v dd v ddq v ddq nc nc f qb3 qb2 v ss v ss v ss zq v ss v ss v ss nc nc g qb5 qb4 v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h qb7 qb6 v ss v ss v ss ep3 v ss v ss v ss nc nc j qb9 qb8 v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq qa8 qa9 m nc nc v ss v ss v ss m3 v ss v ss v ss qa6 qa7 n nc nc v ddq v ddq v dd mch v dd v ddq v ddq qa4 qa5 p nc nc v ss v ss v ss mcl v ss v ss v ss qa2 qa3 r nc nc v ddq v ddq v dd v dd v dd v ddq v ddq qa1 da9 t nc nc v ss nc nc mcl nc nc v ss da8 da7 u nc nc nc a nc (64m) a nc (32m) a nc da6 da5 v nc nc a (2m) a a a1 a a a (4m) da4 da3 w nc nc tms tdi a mcl a tdo tck da2 da1 rev 10 11 x 19 bump bga?14 x 22 mm2 body?1 mm bump pitch?ms-028vbc ? note: users of cmos i/o sigma rams may wish to connect d4, d8, t4, t8 and k4 to v ddq /2 to allow alternate use of hstl i/o sigma rams.
rev: 1.01 11/2000 4/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 8180 s 09 pinout 2m x 9 separate i/o?top view 1 2 3 4 5 6 7 8 9 10 11 a d1 d2 a e2 a, nc (16m) mcl a, nc (8m) e3 a nc nc b d3 d4 nc nc a (x36) w a nc nc nc nc c d5 d6 nc nc a, nc (128m) e1 a (x18) a (x9) nc nc nc d d7 d8 v ss nc nc mcl nc nc v ss nc nc e d9 q1 v ddq v ddq v dd v dd v dd v ddq v ddq nc nc f q3 q2 v ss v ss v ss zq v ss v ss v ss nc nc g q5 q4 v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h q7 q6 v ss v ss v ss ep3 v ss v ss v ss nc nc j q9 q8 v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq cq ck nc v ss mcl v ss nc nc nc nc l nc nc v ddq v ddq v dd m2 v dd v ddq v ddq nc nc m nc nc v ss v ss v ss m3 v ss v ss v ss nc nc n nc nc v ddq v ddq v dd mch v dd v ddq v ddq nc nc p nc nc v ss v ss v ss mcl v ss v ss v ss nc nc r nc nc v ddq v ddq v dd v dd v dd v ddq v ddq nc nc t nc nc v ss nc nc mcl nc nc v ss nc nc u nc nc nc a nc (64m) a nc (32m) a nc nc nc v nc nc a (2m) a a a1 a a a (4m) nc nc w nc nc tms tdi a mcl a tdo tck nc nc rev 1 11 x 19 bump bga?14 x 22 mm2 body?1 mm bump pitch?ms-028vbc ? note: users of cmos i/o sigma rams may wish to connect d4, d8, t4, t8 and k4 to v ddq /2 to allow alternate use of hstl i/o sigma rams.
rev: 1.01 11/2000 5/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 pin description table pin location symbol description type comments a3, a5, a7, a9, b5, b7, u4, u6, u8, v3, v4, v5, v6, v7, v8, v9, w5, w7 a address input (all versions) c7 a address input (x09 and x18 versions) c5, c8 a address input (x09 version only) k3 ck clock input active high k1 cq echo clock output active high k11 cq echo clock output active high (x18 and x36 versions) k2 cq echo clock output active low k10 cq echo clock output active low (x18 and x36 versions) dq data i/o input/output ? c6 e1 chip enable input active low a4, a8 e2 & e3 chip enable input programmable active high or low g6, h6 ep2 & ep3 chip enable program pin input ? g asynchronous output enable input active low w9 tck test clock input active high w4 tdi test data in input ? w8 tdo test data out output ? w3 tms test mode select input ? l6, m6, j6 m2, m3 & m4 mode control pins input ? n6 mch must connect high input active high a6, d6, k6, p6, t6, w6 mcl must connect low input active low (all versions) b3, c9 mcl must connect low input active low (x18 and x36 versions) b8, c4 mcl must connect low input active low (x36 version only)
rev: 1.01 11/2000 6/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 background separate i/o sigma rams have been designed to be closely related to common i/o sigma rams in pinout and overall architecture. the similarities give separate i/o sigma rams a cost advantage by allowing users and vendors to reuse supporting infrastructure and design elements. separate i/o sigma rams come in single and double data rate configurations. because they are designed to operate with both the input data pins and the output data pins operating at full speed all the time, separate i/ o sigma rams produce twice the bandwidth of common i/o srams of the same speed and output bus width. b4, b9, c3, d4, d5, d7, d8, k4, k8, k9, t4, t5, t7, t8, u3, u5, u7, u9 nc no connect ? not connected to die or any other pin (all versions) a10, a11, b8, b10, b11, c4, c10, c11, d10, d11, e10, e11, f10, f11, g10, g11, h10, h11, j10, j11, l1, l2, m1, m2, n1, n2, p1, p2, r1, r2, t1, t2, u1, u2, v1, v2, w1, w2 nc no connect ? not connected to die or any other pin (x09 and x18 versions) c5, c8 nc no connect ? not connected to die or any other pin (x18 and x36 versions) b3, c9, k10, k11, l10, l11, m10, m11, n10, n11, p10, p11, r10, r11, t10, t11, u10, u11, v10, v11, w10, w11 nc no connect ? not connected to die or any other pin (x18 version only) c7 nc no connect ? not connected to die or any other pin (x36 version only) b6 w write input active low e5, e6, e7, g5, g7, j5, j7, l5, l7, n5, n7, r5, r6, r7 v dd core power supply input 1.8 v nominal e3, e4, e8, e9, g3, g4, g8, g9, j3, j4, j8, j9, l3, l4, l8, l9, n3, n4, n8, n9, r3, r4, r8, r9 v ddq output driver power supply input 1.8 v or 1.5 v nominal d3, d9, f3, f4, f5, f7, f8, f9, h3, h4, h5, h7, h8, h9, k5, k7, m3, m4, m5, m7, m8, m9, p3, p4, p5, p7, p8, p9, t3, t9 v ss ground input ? f6 zq output impedance control input ? pin description table pin location symbol description type comments
rev: 1.01 11/2000 7/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 separate i/o srams, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. therefore, the sigma ram separate i/o interface and truth table are optimized for alternating reads and writes. separate i/ o srams are unpopular in applications where multiple reads multiple writes are needed because burst read or write transfers from separate i/o srams cut the ram?s bandwidth in half. separate i/o sigma rams offer users the simplest possible control scheme for back-to-back read-write operations. although the separate i/o sigma ram family of pinouts has been designed to support single and double data rate options, not all sigma ram implementations will support both protocols. the following timing diagrams provide a quick comparison between the sdr and ddr protocol options available in the context of the separate sigma ram standard. this particular data sheet covers the single data rate (sdr) separate i/o sigma ram. the character of the applications for fast synchronous srams in networking systems are extremely diverse. s rams have been developed to address the diverse needs of the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. s rams address each of the bus protocol options commonly found in networking systems. sigma ram bandwidth at 333 mhz clocking configuration x9 x18 x36 x72 units common i/o sdr 3 6 12 24 gb/s common i/o ddr 6 12 24 48 gb/s separate i/o sdr 6 12 24 48 gb/s separate i/o ddr 12 24 48 96 gb/s mode selection truth table standard m2 m3 m4 function in this data sheet? 0 0 0 rfu n/a 0 0 1 rfu n/a 0 1 0 rfu n/a 0 1 1 double data rate no 1 0 0 rfu n/a 1 0 1 rfu n/a 1 1 0 late write, pipelined read yes 1 1 1 rfu n/a
rev: 1.01 11/2000 8/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 separate i/o sigma ram family mode comparison?sdr vs. ddr db0 db1 dd0 dd1 write read write no op write read cq q /e 1 /w d ck address xx b qc0 qc1 c d e f single data rate db0 db1 db2 db3 dd0 dd1 dd2 qc0 qc1 qc2 qc3 cq /e 1 /w d q read write ck address xx b c d e f no op write read write double data rate
rev: 1.01 11/2000 9/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 alternating read-write operations in order to make interface with separate i/o sigma rams as straightforward as possible, the control logic has been optimized specifically for alternate read-write cycles. a separate i/o sigma ram can begin an alternating sequence of reads and writes wit h either a read or a write. the status of the w pin is evaluated at the beginning of the first active cycle after the ram has been deselected via e1 . the status of the w pin is not checked again until the ram has been deselected and reselected via e1 . the user may introduce as few or as many deselect cycles between active cycles as are desired, but the user must inform the ram at the beginning of the first active cycle, via w , whether to restart with a read or write cycle. all address , data, and control inputs (with the exception of ep2, ep3, and the mode pins, m2?m4) are synchronized to rising clock edges. device activation is accomplished by asserting all three of the chip enable inputs ( e1 , e2, and e3). deassertion of any one of the enable inputs will deactivate the device. it should be noted that only deactivation of the ram via e2 and/or e3 (a bank deselect) deactivates the echo clocks, cq1?cqn. conversely, only e1 is used to identify a ?first active cycle? event. read operations read operation will be initiated at the rising edge of clock if the previous cycle was a write and all three chip enables ( e1 , e2, and e3 ) are active. if the previous cycle was a deselect ( e1 high), then all three chip enables must be active and the write enable signal ( w ) must be deasserted high. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the next rising edge of clock the read data is allowed to propagate through th e output register and onto the output pins. write operations write operation will be initiated at the rising edge of clock if the previous cycle was a read and all three chip enables ( e1 , e2, and e3 ) are active. if the previous cycle was a deselect ( e1 high), then all three chip enables must be active and the write enable signal ( w ) must be asserted low. separate i/o sigma rams employ an ?late write? protocol, meaning the address input and the write command are due into the ram on the same rising edge of clock, but data in is due into the ram on the next rising edge of clock . separate i/o sigma rams accumulate the input data in a register and then feeds the accumulated data into the array at the first opportunity. separate i/o sigma rams are fully coherent, which is to say, if the user asks for data just written to the ram, the most recent copy of the data will be read directly out of the holding registers rather than from the array (which contains stale data).
rev: 1.01 11/2000 10/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 single data rate separate i/o sigma ram with first cycle write single data rate separate i/o sigma ram with first cycle read db0 db1 dd0 dd1 write read write no op write read cq q /e 1 /w d ck address xx b qc0 qc1 c d e f dc0 dc1 de0 write read no op read write read ck address xx b c d e f /e 1 /w d q qb0 qb1 cq qd0
rev: 1.01 11/2000 11/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 special functions echo clock s rams feature echo clocks, cq1,cq2, cq 1 , and cq2 that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, ck. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with the rest of the data output drivers. sigma rams provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs ( cq1 and cq2 ). it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. echo clocks are alway s active unless deselected by e2 or e3. the deselection of echo clock drivers is always pipelined to the same degree as output dat a. deselection of the ram via e1 does not deactivate the echo clocks. programmable enables s rams feature two user-programmable chip enable inputs, e2 and e3. the sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, ep2 and ep3. for example, if ep2 is held at v dd , e2 functions as an active high enable. if ep2 is held to v ss , e2 functions as an active low chip enable input. programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming the enable inputs of four s rams in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four s rams can be made to look like one larger ram to the system. example four bank depth expansion schematic a ck e1 e2 e3 w a 0 ?a n ck w q 0 ?q n d 0 ?d n bank 0 bank 1 bank 2 bank 3 bank enable truth table ep2 ep3 e2 e3 bank 0 vss vss active low active low bank 1 vss vdd active low active high bank 2 vdd vss active high active low bank 3 vdd vdd active high active high e1 a n ? 1 a n a 0 ?a n-2 a n-1 a n a 0 - a n-2 a n-1 a n a 0 - a n-2 a n-1 a n a 0 - a n-2 q d a ck e2 e3 w q d a ck e2 e3 w q d a ck e2 e3 w q d e1 e1 e1
rev: 1.01 11/2000 12/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 echo clock control in two banks of sdr separate i/o sigma rams it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. in some applications it may be appropriate to pause between banks?to deselect both rams with e1 before resuming read operations. an e1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the ram in bank 2 to issue at least one clock before it is needed. dc0 dc1 de0 de1 note: 1 e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false. 2 reads or writes launched in a bank continue in the same bank. bank 1 bank 1 no op read write read write read write - bank 2 bank 2 bank 2 bank 1 qd1 qd0 qd1 g f qb1 q bank 1 + q bank 2 qb1 qb0 qb0 cq bank 1 cq1 + cq2 cq bank 2 q bank 2 /e2 bank 1 e2 bank 2 q bank 1 /e 1 /w d bank 1 d bank 2 c qd0 d e ck address xx b
rev: 1.01 11/2000 13/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 .separate i/o sigma ram bank switch with e1 deselect flxdrive? output driver impedance control the zq pin allows selection between s ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications. see the output driver characteristics chart for details. df0 df1 dc0 dc1 note: 1 e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false. 2 reads or writes launched in a bank continue in the same bank. qe1 h i write bank 1 qg0 qg0 qe1 qe0 cq bank 1 cq bank 2 cq1 + cq2 q bank 1 + q bank 2 qb0 qb1 q bank 2 qb0 qb1 d bank 2 /e2 bank 1 e2 bank 2 q bank 1 qe0 g /e 1 /w d bank 1 c d e f ck address xx b read write read - bank 2 bank 2 both bank 1 bank 1 bank 1 no op read write deselect
rev: 1.01 11/2000 14/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 separate i/o sdr sigma ram truth table ck previous state control inputs next state d (t n + 1 ) d (t n + 2 ) q (t n + 1 ) q (t n + 2 ) e1 e w cq (t n + 1 ) cq (t n + 2 ) - deselect, bank deselect, deselect read, deselect write 1 f x bank deselect x ? hi-z ? - write 1 f x bank deselect d1 ? hi-z ? - read 1 f x bank deselect x ? q1 ? cq1 - deselect, bank deselect, deselect write 1 t x deselect x ? hi-z ? cq0 - deselect read 1 t x deselect x ? hi-z ? - write 1 t x deselect d1 ? hi-z ? cq0 - read 1 t x deselect x ? q1 ? cq1 - deselect, bank deselect 0 f 0 deselect write x x hi-z ? - deselect read 0 f x deselect write x x hi-z ? - read 0 f x deselect write x x q1 ? cq1 - deselect, bank deselect 0 f 1 deselect read x ? hi-z hi-z - deselect write 0 f x deselect read x ? hi-z hi-z - write 0 f x deselect read d1 ? hi-z hi-z - deselect, bank deselect 0 t 0 write d0 d1 hi-z ? cq0 - deselect read 0 t x write d0 d1 hi-z ? - read 0 t x write d0 d1 q1 ? cq1 - deselect, bank deselect 0 t 1 read x ? q0 q1 cq0 cq1 - deselect write 0 t x read x ? q0 q1 cq0 cq1 - write 0 t x read d1 ? q0 q1 cq0 cq1 notes: 1. x = don?t care, h = high, l = low. e = t (true) if e2 = 1 and e3 = 0; e = f (false) if e2 = 0 or e3 = 1. 2. d0 and d1 are the first and second data input transfers in a write. 3. q0 and q1 are the first and second data output transfers in a read. 4. cq0 and cq1 are the echo clocks associated with the first and second data transfers. 5. ??? indicates that the input needed or driver state is determined by a subsequent operation.
rev: 1.01 11/2000 15/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 separate i/o sigma ram control state diagram deselect read write deselect read deselect write 1,t,x 0,t,0 0,t,1 0,f,x 0,f,x 0,t,x 0,t,x 0,f,x 0,f,x 0,t,x 0,t,x key: x,x,x = e1 , e, w where e = t (true) if e2 = 1 and e3 = 0; e = f (false) if e2 = 0 or e3 = 1 bank deselect 1,f,x 1,t,x 0,f,0 1,t,x 1,t,x 0,f,1 1,f,x 1,t,x 1,f,x 1,f,x 1,f,x 0,t,0 0,t,1 0,f,0 0,f,1
rev: 1.01 11/2000 16/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to rec- ommended operating conditions. exposure to conditions exceeding the recommended operating conditions, for an extended period of time, may affect reliability of this component. recommended operating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to v dd v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.5 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.8v i/o supply voltage v ddq 1.7 1.8 v dd v 1 1.5v i/o supply voltage v ddq 1.4 1.5 1.6v v 1 ambient temperature (commercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ?40 25 85 c 2 notes: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6 v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the power supplies need to be powered up in the following sequence: v dd , v ddq , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . 3. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evalu- ated for worst case in the temperature range marked on the device.
rev: 1.01 11/2000 17/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 note: this parameter is sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. cmos i/o dc input characteristics parameter symbol min. typ. max. unit notes cmos input high voltage v ih 0.65 * v ddq ? v dd + 0.3 v 2 cmos input low voltage v il ?0.3 ? 0.35 * v ddq v 2 note: for devices supplied with cmos input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. capacitance (t a = 25 o c , f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja tbd c/w 1,2 junction to ambient (at 200 lfm) four r q ja tbd c/w 1,2 junction to case (top) ? r q jc tbd c/w 3 20% tkc v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 1.0 v 50% v dd v il
rev: 1.01 11/2000 18/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 notes: 1. test conditions as specified with output loading as shown unless otherwise noted. ac test load diagrams ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua mode pin input current i in m v dd 3 v in 3 v il 0 v v in v il ?100 ua ?2 ua 2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua selectable impedance cmos output driver dc electrical characteristics parameter symbol test conditions min. max notes low drive output high voltage v ohl i ohl = ?4 ma v ddq ? 0.4 v 1 low drive output low voltage v oll i oll = 4 ma ? 0.4 v 1 high drive output high voltage v ohh i ohh = ?8 ma v ddq ? 0.4 v 2 high drive output low voltage v olh i olh = 8 ma ? 0.4 v 2 dq vt = v ddq /2 50 w ac test load a dq ac test load b 5 pf
rev: 1.01 11/2000 19/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 operating currents parameter test conditions symbol -333 -300 -275 -250 units 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current e1 v il max. tkhkh 3 tkhkh min. all other inputs v il 3 v in 3 v ih i dd p pipeline tbd tbd tbd tbd tbd tbd tbd tbd ma bank deselect current e2 or e3 false tkhkh 3 tkhkh min. all other inputs v il 3 v in 3 v ih i sb1 pipeline tbd tbd tbd tbd tbd tbd tbd tbd ma chip disable current e1 3 v ih min. tkhkh 3 tkhkh min. all other inputs v il 3 v in 3 v ih i sb2 pipeline tbd tbd tbd tbd tbd tbd tbd tbd ma cmos deselect current device deselected all inputs v ss + 0.10 v 3 v in 3 v dd ? 0.10 v i dd3 pipeline tbd tbd tbd tbd tbd tbd tbd tbd ma note: power measured with outputs disconnected.
rev: 1.01 11/2000 20/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 ac electrical characteristics parameter symbol -333 -300 -275 -250 unit notes min max min max min max min max clock cycle time tkhkh 3.0 ? 3.3 ? 3.6 ? 4.0 ? ns ? clock high to output valid tkhqv ? 1.6 ? 1.8 ? 1.9 ? 2.1 ns ? clock high to output in high-z tkhqz 0.5 1.6 0.5 1.8 0.5 1.9 0.5 2.1 ns 1 clock high to output invalid tkhqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output in low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 clock high to echo clock low-z tkhcx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 2, 4 clock high to echo clock high tkhch 0.6 1.5 0.6 1.7 0.6 1.8 0.6 2.0 ns 4 clock low to echo clock low tklcl 0.6 1.7 0.6 1.8 0.6 2.0 0.6 2.2 ns 4 output invalid to echo clock high tchqx ? ?0.5 ? ?0.6 ? ?0.6 ? ?0.7 ns 2 echo clock high to output valid tchqv ? 0.5 ? 0.6 ? 0.6 ? 0.7 ns 2 clock high to echo clock high-z tkhcz 0.5 1.5 0.5 1.7 0.5 1.8 0.5 2.0 ns 1, 2 clock high time tkhkl 1.2 ? 1.3 ? 1.4 ? 1.6 ? ns ? clock low time tklkh 1.2 ? 1.3 ? 1.4 ? 1.6 ? ns ? address valid to clock high tavkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to address don?t care tkhax 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? enable valid to clock high tevkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to enable don?t care tkhex 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? write valid to clock high twvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to write don?t care tkhwx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? data in valid to clock high tdvkh 0.6 ? 0.7 ? 0.7 ? 0.8 ? ns ? clock high to data in don?t care tkhdx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1. 4. tested using ac test load b
rev: 1.01 11/2000 21/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 timing parameter key - read cycle timing tkhqx1 tkhqv tavkh tkhax tkhqx tkhqz tkhch ck a q tkhkh tklkh tkhkl a b c qa cq tchqv tqxch tkhcx1 tklcl tkhcz = cq high z (pipelined)
rev: 1.01 11/2000 22/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 timing parameter key - control and data in timing jtag port operation overview the jtag port on this ram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. unlike jtag implementations that have been common among sram vendors for the last several years, this implementation does offer a form of extest, known as clock assisted extest, reducing or eliminating the ?hand coding? that has been required to overcome the test program compiler errors caused by previous non-compliant implementations. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to v dd . tdo should be left unconnected. tkhnx tnvkh tavkh tkhax ck a a b c e1 , w, d (data in) tkhdx tdvkh note: tnvkh = tevkh, twvkh, etc. and tkhnx = tkhex, tkhwx, etc. da0 da1 e2, e3
rev: 1.01 11/2000 23/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 jtag port registers overview the various jtag registers, refered to as tap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle , or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed thr ough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between th e device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the boundary scan register. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while t ms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up.
rev: 1.01 11/2000 24/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990?the standard (public) instructions, and device specifi c (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1- compliant because some of the mandatory instructions are uniquely implemented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data or control signals into the ram or to preload the i/o buffers.t his device will not perform intest or the preload portion of the sample/preload command. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code p r e s e n c e r e g i s t e r bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x09 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.01 11/2000 25/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded wit h 01. when the controller is moved to the shift-ir state, the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register, the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing o f other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruc - tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bou ndary scan register. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable in puts will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the tap?s i nput data capture set-up plus hold time (tts plus tth ). the ram?s clock inputs need not be paused for any other tap operation except capt uring the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan registe r between select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
rev: 1.01 11/2000 26/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction register has the same effect as the pause-dr com- mand. this functionality is not standard 1149.1-compliant. extest (extest-a) extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length i t may be in the device, is loaded with all logic 0s. the extest implementation in this device does not, without further user intervention, a ctually move the contents of the scan chain onto the ram?s output pins. therefore this device is not strictly 1149.1-compliant. nevertheless, this ram?s tap does respond to an all 0s instruction, extest (000), by overriding the ram?s control inputs and activating the data i/o out put drivers. the ram?s main clock (ck) may then be used to transfer boundary scan register contents associated with each i/o from the scan re gister to the ram?s output drivers and onto the i/o pins. a single ck transition is sufficient to transfer the data, but more transitio ns will do no harm. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z ) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest-a 000 places the boundary scan register between tdi and tdo. this ram implements an clock assisted extest function. *not 1149.1 compliant * 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data and clock output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this ram does not implement 1149.1 preload function. *not 1149.1 compliant * 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.01 11/2000 27/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v iht 0.65 * v dd v dd +0.3 v 1 test port input low voltage v ilt ?0.3 0.35 * v dd v 1 tms, tck and tdi input leakage current i in th ?100 2 ua 2 tms, tck and tdi input leakage current i in tl ?2 2 ua 3 tdo output leakage current i olt ?2 2 ua 4 test port output high voltage v oht v ddq ? 100 mv ? v 5, 6 test port output low voltage v olt ? 100 mv v 7 notes: 1. input under/overshoot voltage must be ?1 v < vi < v dd + 1 v with a pulse width not to exceed 20% ttkc. 2. v dd 3 v in 3 v il 3. 0 v v in v il 4. output disable, v out = 0 to v dd 5. the tdo output driver is served by the v dd supply. 6. i oh = ?100 ua 7. i ol = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 200 mv input low level 200 mv input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 dq v t = v dd /2 50 w jtag port ac test load
rev: 1.01 11/2000 28/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 20 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 10 ? ns tck low pulse width ttkl 10 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.01 11/2000 29/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 output driver characteristics tbd
rev: 1.01 11/2000 30/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 package dimensions?209-bump bga 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min. typ. max. units a ? ? 1.7 mm a1 0.40 0.50 0.60 mm a2 0.31 0.36 0.38 mm b 0.50 0.60 0.70 mm d 21.9 22.0 22.1 mm d1 ? 18.0 (bsc) ? mm e 13.9 14.0 14.1 mm e1 ? 10.0 (bsc) ? mm e ? 1.00 (bsc) ? mm ddd ? 0.15 ? mm rev 1.2 a a1 a2 ? b e e e e 1 d1 d ddd bottom view side view
rev: 1.01 11/2000 31/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 ordering information?gsi sigma ram org part number 1 type package speed (mhz) t a 3 512kx 36 gs818 0 s 36b-333 separate i/o s ram 1 mm pitch, 209-pin bga 333 c 512kx 36 gs818 0 s 36b-300 separate i/o s ram 1 mm pitch, 209-pin bga 300 c 512kx 36 gs818 0 s 36b-275 separate i/o s ram 1 mm pitch, 209-pin bga 275 c 512kx 36 gs818 0 s 36b-250 separate i/o s ram 1 mm pitch, 209-pin bga 250 c 512kx 36 gs818 0 s 36b-333i separate i/o s ram 1 mm pitch, 209-pin bga 333 i 512kx 36 gs818 0 s 36b-300i separate i/o s ram 1 mm pitch, 209-pin bga 300 i 512kx 36 gs818 0 s 36b-275i separate i/o s ram 1 mm pitch, 209-pin bga 275 i 512kx 36 gs818 0 s 36b-250i separate i/o s ram 1 mm pitch, 209-pin bga 250 i 1m x 18 gs818 0 s 18b-333 separate i/o s ram 1 mm pitch, 209-pin bga 333 c 1m x 18 gs818 0 s 18b-300 separate i/o s ram 1 mm pitch, 209-pin bga 300 c 1m x 18 gs818 0 s 18b-275 separate i/o s ram 1 mm pitch, 209-pin bga 275 c 1m x 18 gs818 0 s 18b-250 separate i/o s ram 1 mm pitch, 209-pin bga 250 c 1m x 18 gs818 0 s 18b-333i separate i/o s ram 1 mm pitch, 209-pin bga 333 i 1m x 18 gs818 0 s 18b-300i separate i/o s ram 1 mm pitch, 209-pin bga 300 i 1m x 18 gs818 0 s 18b-275i separate i/o s ram 1 mm pitch, 209-pin bga 275 i 1m x 18 gs818 0 s 18b-250i separate i/o s ram 1 mm pitch, 209-pin bga 250 i 2mx 9 gs818 0 s 09b-333 separate i/o s ram 1 mm pitch, 209-pin bga 333 c 2mx 9 gs818 0 s 09b-300 separate i/o s ram 1 mm pitch, 209-pin bga 300 c 2mx 9 gs818 0 s 09b-275 separate i/o s ram 1 mm pitch, 209-pin bga 275 c 2mx 9 gs818 0 s 09b-250 separate i/o s ram 1 mm pitch, 209-pin bga 250 c 2mx 9 gs818 0 s 09b-333i separate i/o s ram 1 mm pitch, 209-pin bga 333 i 2mx 9 gs818 0 s 09b-300i separate i/o s ram 1 mm pitch, 209-pin bga 300 i 2mx 9 gs818 0 s 09b-275i separate i/o s ram 1 mm pitch, 209-pin bga 275 i 2mx 9 gs818 0 s 09b-250i separate i/o s ram 1 mm pitch, 209-pin bga 250 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs818x36b-300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
rev: 1.01 11/2000 32/32 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. a advanced information gs8180 s 09/18 /36 b-333/300/275/250 revision history rev. code: old; new types of changes format or content revisions 8180s091836_r1; 8180s091836_r1_01 format ? updated format to comply with technical publications standards ? id register contents updated on page 24

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